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july 2013 ? 2012 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support fan54040 fan54047 usb - otg, 1.55 a, li - ion switching charger with power path and 2.3 a production test support features ? fully integrated, high - efficiency charger for single - cell li - ion and li - polymer battery p acks ? power path circuit ensures fast system startup with a dead battery when vbus is connected ? 1.55 a maximum charge current ? float voltage accuracy: - ? 0.5% at 25c - ? 1% from 0 to 125c ? ? 5% input and charge current regulation accuracy ? temperature - sense input prevents auto - charging for jeita compliance ? thermal regulation and shutdown ? 4.2 v at 2.3 a production test mode ? 5 v, 500 ma boost mode for usb otg ? 2 8 v absolute maximum input voltage ? 6 v maximum input operating voltage ? programmable through high - speed i 2 c interface (3.4 mb/s) with fast mode plus compatibility - input current - fast - charge / termination current - float voltage - termination enable ? 3 m h z synchronous buck pwm controller with wide duty cycle range ? small footprint 1 ? h external inductor ? safety timer with reset control ? dynamic input voltage control ? very low battery current when charger inactive applications ? cell phones, smart phones, pdas ? tablet, portable media players ? gaming device, digital cameras description the fan5404x family includes i 2 c controlled 1.55 a usb - compliant switch - mode charger s with power path operation and usb otg boost operation . integrated with the charger , the ic supports production test mode, which provides 4.2 v at up to 2.3 a to the system. to facilitate fast system startup, the ic includes a p ower p ath circuit, which disconnects the battery from the system rail, ensuring that the system can power up quickly following a vbus conne ction. the p ower p ath circuit ensures that the system rail stays up when the charger is plugged in, even if the battery is dead or shorted. the charging parameters and operating modes are programmable through an i 2 c interface that operates up to 3.4 mbps. the charger and boost regulator circuits switch at 3 mhz to minimize the size of external passive components. the fan5404x provides battery charging in three phases: conditioning, constant current, and constant voltage. the integrated circuit automaticall y restarts the charge cycle when the battery falls below a voltage threshold. if the input source is removed, the ic enters a high - impedance mode blocking battery current from leaking to the input. charge status is reported back to the host through the i 2 c port. dynamic i nput v oltage c ontrol prevents a weak adapter s voltage from collapsing, ensuring charging capability from such adapters. the fan5404x is available in a 25 - bump, 0.4 mm pitch , wlcsp package . figure 1 . typical application all trademarks are the property of their respective owners. s w s y s t e m l o a d l 1 q 5 s d a s c l v b u s c b u s v b a t s y s g a t e c s y s e x t e r n a l p m o s p o k _ b i l i m d i s p g n d s t a t a g n d + p m i d c m i d c b a t n t c r e f r r e f c r e f t b a t t e r y f a n 5 4 0 4 x
? 201 2 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 2 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support ordering information part number temperature range package pn bits: ic_info[ 5 :3] packing method fan 54040 ucx - 40 to 85c 25 - bump, wafer - level chip - scale package ( wlcsp ) , 0.4 mm pitch 00 0 tape and reel fan 54041 ucx 001 fan 54042 ucx ( 1 ) 010 fan 54045 ucx ( 1 ) 101 fan54046ucx ( 1 ) 110 fan 54047 ucx 110 note: 1. contact fairchild sales for availability. table 1 . feature c omparison s ummary part number slave address automatic charge battery absent behavior e1 pin fan 54040 1101011 yes o ff pok_b fan 54041 1101011 no o ff pok_b fan 54042 1101011 yes o n pok_b fan 54045 1101011 no o ff ilim fan54046 1101011 no o n ilim fan 54047 1101011 yes o n ilim
? 201 2 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 3 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support block diagram pmid q1a q1b greater than v bat on off less than v bat off on sys q4a q4b greater than v bat on off less than v bat off on figure 2 . ic and system block diagram table 2 . recommended external components component description vendor parameter typ. unit l1 1 ? h, 20%, 2. 2 a , 2016 taiyo yuden makk2016t1r0m or equivalent l 1.0 ? h dcr ( s eries r) 7 5 m ? c bat , c sys 10 ? f, 20%, 6.3 v, x5r, 0603 murata : grm188r60j106m tdk: c1608x5r0j106m c 10 ? f c mid 4.7 ? f, 10%, 6.3 v, x5r, 0 603 murata : grm188r60j475k tdk: c1608x5r0j475k c ( 2 ) 4.7 ? f c bus , 1.0 ? f, 10%, 25 v, x 5 r, 0603 murata grm188r61e105k tdk:c1608x5r1e105m c 1.0 ? f q5 pmos , 12 v, 16 m ? , mlp2x2 fairchild fdma905p r ds (on) 16 m ? c ref 1 ? f, 10%, 6.3 v, x5r, 0402 c 1.0 ? f note: 2. 6.3 v rating is sufficient for c mid since pmid is protected from over - voltage surges on vbus by q3. s w s y s t e m l o a d q 2 l 1 q 5 s d a s c l v b u s c b u s v b a t s y s g a t e c s y s e x t e r n a l p m o s q 3 p o k _ b i l i m c h a r g e p u m p q 3 d i s p g n d p g n d s t a t a g n d + q 1 b q 1 a q 1 p m i d p w m m o d u l a t o r c c a n d c v b a t t e r y c h a r g e r c m i d c b a t n t c r e f r r e f t e m p s e n s e i 2 c i n t e r f a c e l o g i c a n d c o n t r o l c r e f i b u s & v b u s c o n t r o l v b u s o v p p o w e r o k q 4 b q 4 a q 4 t b a t t e r y
? 201 2 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 4 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support pin configuration figure 3 . top view figure 4 . bottom view pin definitions pin # name description a1 sda i 2 c interface serial data . this pin should not be left floating. b1 scl i 2 c i nterface s erial c lock . this pin should not be left floating. c1 dis disable . if this pin is held high , q1 and q3 are turned off , creating a high z condition at vbus and the pwm converter is disabled . d1 stat status . open - drain output indicating charge status. the ic pulls this pin low when charge is in pro gr ess ; can be used to signal the host processor when a fault condition occurs . e1 pok_b power ok (fan54040 - 2) . open - drain output that pulls low when vbus is plugged in and the battery has risen above v lowv . this signal is used to signal the host processor that it can begin to draw significant current. e1 ilim input current limit (FAN54045 - 7 ) . controls input current limit in a uto - c harge m ode. wh en low , input current is limited to 100 ma max imum . when high , input current is limited to 500 ma. in 32 - s econd m ode, the input current limit is set by the i bus lim bits. a2 C d2 pgnd power g round . power return for gate drive and power transistors. the connection from this pin to the bottom of c mid should be as short as possible. e2 a gnd analog g round . all ic signals are referenced to this node. a3 C c3 sw switching node . connect to output inductor . d3 C e3 sys system supply . output voltage of the switching charger and input to the power path controller. bypass sys to pgnd with a 10 f capacitor. a4 C c4 pmid power i nput v oltage . power input to the charger regulator, bypass point for the input current sense. bypass with a minimum of a 4.7 ? f, 6.3 v capacitor to pgnd . d4 C e4 vbat battery voltage . connect to the positive (+) terminal of the battery pack. bypass with a 10 ? f capacitor to pgnd . vbat is a power path connection. a5 C b5 vbus charger input voltage and usb - otg output voltage. bypass with a 1 ? f capacitor to pgnd . c5 gate external mosfet gate . this pin controls the gate of an external p - channel mosfet transistor used to augment the internal ideal diode. the source of the p - channel mosfet should be connected to sys and the drain should be connected to vbat. d5 ntc thermistor input . the ic compares this node with taps on a resistor divider from ref to inhibit auto - charging when the battery temperature is outside of permitted fast - charge limits . e5 ref reference voltage . ref is a 1.8 v regulated output . r e f n t c p g n d g a t e d i s s t a t s c l s d a p o k _ b s y s v b a t s w p m i d v b u s a g n d a 1 a 2 a 3 a 4 a 5 b 1 b 3 b 2 b 4 b 5 c 1 c 3 c 2 c 4 c 5 d 1 d 3 d 2 d 4 d 5 e 1 e 3 e 2 e 4 e 5 c 1 b 1 a 1 c 5 b 5 a 5 a 4 c 4 d 1 d 5 d 4 b 4 e 1 e 5 e 4 c 3 b 3 a 3 a 2 c 2 d 3 d 2 b 2 e 3 e 2
? 201 2 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 5 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recomme nded. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v bus voltage on vbus pin continuous - 0.3 2 8 .0 v pulsed, 100 ms max imum n on - r epetitive - 1.0 v i voltage on pmid voltage pin C pins C o voltage on other pins C ( 3 ) v maximum v bus slope a bove 5.5 v when boost or charger a ctive 4 v/ ? ( 4 ) human body model per jesd22 - a114 2000 v charged device model per jesd22 - c101 500 iec 61000 - 4 - 2 system esd usb connector pins (v bus to gnd ) air gap 15 kv contact 8 t j junction temperature C stg storage temperature C l lead soldering temperature, 10 seconds +260 c note : 3. lesser of 6.5 v or v i + 0.3 v. 4. guaranteed if c bus 1f and c mid 4.7f . recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. max. unit v bus supply voltage 4 6 v v bat(max) maximum b attery v oltage when boost enabled 4.5 v negative vbus s lew r ate during vbus s hort c ircuit , c mid < 4.7 ? s ee vbus short w hile c harging t a < 60 c 4 v/ ? a > 60 c 2 t a ambient temperature C j junction temperature (see thermal regulation and p rotection section) C thermal properties junction - to - ambient thermal resistance is a function of application and board layout. this data is measured with four - layer 2 s2p boards in accordance to jedec standard jesd51. special attention must be paid not to exceed junction temperature t j(max) at a given ambient temperat ur e t a . for measured data , see table 18 . symbol parameter typical unit ? ja junction - to - ambient thermal resistance (see also figure 18 ) 5 0 c/w ? j b junction - to - pcb thermal resistance 20 c/w dt dv bus dt dv bus ?
? 201 2 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 6 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support electrical specifications unless otherwise specified : according to the c ircuit of figure 1 ; recommended operating temperature range for t j and t a ; v bus = 5.0 v; hz_mode ; opa_mode = 0 ; ( c harge m ode) ; scl, sda = 0 or 1.8 v ; and t ypical values are for t j = 25c. symbol parameter conditions min. typ. max. unit power supplies i vbus vbus c urrent v bus > v bus(min) , pwm s witching 10 ma v bus > v bus(min) ; v bat > v oreg i buslim = 100 ma 2.5 ma 0c < t j < 85c, hz_mode = 1 v bat < v lowv , 32s mode , i reg = 0 280 ? bat_hz battery discharge current in h igh - i mpedance m ode dis = 1, or hz_mode = 1, v bus = 0, 5 v or floating, v bat = 4.2 v < 1 10 ? bus_hz battery leakage current to v bus in h igh - i mpedance m ode dis = 1, or hz_mode = 1, v bus s horted to g round , v bat =4.2 v - 5 .0 - 0.2 ? ? charger voltage regulation v oreg charge voltage r ange 3.5 4.4 v charge voltage accuracy t a = 25c C j = 0 to 125c C charging current regulation i ochrg output charge current range v lowv < v bat < v oreg io_level=0 550 1 5 50 ma io_level=1 290 340 390 ma charge current accuracy io_level = 0 C weak battery detection v lowv weak b attery t hreshold r ange 3.4 3.7 v weak b attery t hreshold a ccuracy C logic levels : dis, sda, scl v ih h igh - level input voltage 1.05 v v il l ow - level input voltage 0.4 v i in input bias current input t ied to gnd or v bus 0.01 1.00 ? charge termination detection i (term) termination c urrent r ange v bat > v oreg C rch , v bus > v slp 50 400 ma termination c urrent a ccuracy i term setting < 100 ma C term setting > 2 00 ma C power path (q4) control i lin power path max. charge current io_level=1 290 340 390 ma i bus lim > 01, i ocharge < 02 io_level=0 400 450 510 ma i bus lim > 01, i ocharge > 02 io_level=0 650 725 800 ma v thsys vbat to sys threshold for q4 and gate transition while charging (sys - vbat) falling C C C production test mode v bat (ptm) production test output voltage 1 ma < i bat < 2 a, v bus = 5.5 v 4.116 4.2 00 4.284 v i bat (ptm) production test output current 20% duty with max . period 10 ms 2.3 a continued on the following page
? 201 2 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 7 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support electrical specifications (continued) unless otherwise specified : according to the c ircuit of figure 1 ; recommended operating temperature range for t j and t a ; v bus = 5.0 v; hz_mode ; opa_mode = 0 ; ( c harge m ode) ; scl, sda = 0 or 1.8 v ; and t ypical values are for t j = 25c. symbol parameter conditions mi n. typ. max. unit input power source detection t1 t1 (0c) temperature t hreshold 71.9 73.9 75.9 % of v ref t2 t1 (10c) t emperature threshold 62.6 64.6 66.6 t3 t1 (45c) temperature t hreshold 31.9 32.9 34.9 t4 t1 (60c) temperature threshold 21.3 23.3 25.3 input power source detection v in(min)1 vbus input voltage rising to initiate and pass vbus validation 4.29 4.42 v v in(min)2 min imum vbus during charge during charging 3.71 3.94 v t vbus_valid vbus validation time 30 ms v bus control loop v bus lim vbus loop setpoint accuracy C input current limit i bus lim charger input current limit threshold i buslim s et to 100 ma 88 93 98 ma i buslim s et to 500 ma 450 475 500 v ref bias generator v ref bias regulator voltage v bus > v in(min) 1.8 v short - circuit current limit 2.5 ma battery recharge threshold v rch recharge threshold below v (oreg) 100 120 150 mv ? bat falling below v rch threshold 130 ms stat , pok_b output v stat(ol) stat output low i stat = 10 ma 0.4 v ? stat(oh) stat high leakage current v stat = 5 v 1 ? ? battery detection i detect battery detection current before charge done (sink current) ( 5 ) begins after termination detected and v bat < v oreg C rch C detect battery detection time 262 ms sleep comparator v slp sleep - mode entry threshold, v bus C bat 2.3 v < v bat < v oreg , v bus falling 0 0.04 0.10 v power switches (see figure 2 ) r ds(on) q3 on resistance ( vbus to pmid) i in(limit) = 500 ma 180 250 m ? bat =4. 2 v 70 100 m ? sync synchronous to non - synchronous current cut - off threshold ( 6 ) low - side mosfet (q2) cycle - by - cycle current limit 140 ma continued on the following page
? 201 2 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 8 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support electrical specifications (continued) unless otherwise specified : according to the c ircuit of figure 1 ; recommended operating temperature range for t j and t a ; v bus = 5.0 v; hz_mode ; opa_mode = 0 ; ( c harge m ode) ; scl, sda = 0 or 1.8 v ; and t ypical values are for t j = 25 c. symbol parameter conditions min. typ. max. unit charger pwm modulator f sw oscillator frequency 2.7 3.0 3.3 mhz d max maximum duty cycle 100 % d min minimum duty cycle 0 % boost mode operation (opa_mode = 1, hz_mode = 0) v boost boost o utput v oltage at vbus 2.5 v < v bat < 4.5 v, i load from 0 to 200 ma 4.80 5.07 5. 20 v 3 . 0 v < v bat < 4.5 v, i load from 0 to 5 00 ma 4. 77 5.07 5. 20 i bat(boost) boost m ode q uiescent c urrent pfm m ode, v bat = 3.6 v, i load = 0 250 3 5 0 ? limpk(bst) q2 p eak c urrent l imit 1 35 0 1 55 0 1 95 0 ma ? bst minimum b attery v oltage for b oost o peration while b oost a ctive 2. 3 2 v to s tart b oost r egulator 2. 4 8 2.70 vbus load resistance r vbus vbus to pgnd r esistance normal operation 5 00 k ? ? protection and timers vbus ovp vbus over - v oltage s hutdown v bus r ising 6.09 6.29 6.49 v hysteresis v bus f alling 100 mv i limpk(chg) q1 c ycle - by - c ycle p eak c urrent l imit c harge m ode 3 a ? short battery s hort - c ircuit t hreshold v bat r ising 1.95 2.00 2.05 v hysteresis 100 mv i short linear c harging c urrent v bat < v short power path 13 ma linear 30 t shutdwn thermal s hutdown t hreshold ( 7 ) t j r ising 145 c hysteresis ( 7 ) t j f alling 25 t cf thermal r egulation t hreshold ( 7 ) c harge c urrent r eduction b egins 120 c t int detection i nterval 2.1 s t 32s 32 - s econd t imer ( 8 ) charger e nabled 20.5 25.2 28 .0 s charger d isabled 18 .0 25.2 34 .0 t 15min 15 - m inute t imer 15 - m inute m ode (fan 5404 0 , f an 5404 2 , fan54046 , fan54047 ) 12 .0 13.5 15 .0 min ? lf low - frequency timer a ccuracy charger i nactive C note s : 5. negative current is current flowing from the battery to vbus (discharging the battery). 6. q2 always turns on for 60 ns, then turns off if current is below i sync . 7. guaranteed by design; not tested in production. 8. this tolerance (%) applies to all timers on the ic, including soft - start and deglitching timers.
? 201 2 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 9 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support i 2 c timing specifications guaranteed by design. symbol parameter conditions min. typ. max. unit f scl scl clock frequency standard mode 100 khz fast mode 400 fast mode plus 1000 high - speed mode, c b < 100 pf 3400 high - speed mode, c b < 400 pf 1700 t buf bus - free time between stop and start conditions standard mode 4.7 ? hd;sta start or repeated start hold time standard mode 4 ? low scl low period standard mode 4.7 ? ? ? b < 100 pf 160 ns high - speed mode, c b < 400 pf 320 ns t high scl high period standard mode 4 ? b < 100 pf 60 ns high - speed mode, c b < 400 pf 120 ns t su;sta repeated start setup time standard mode 4.7 ? su;dat data setup time standard mode 250 ns fast mode 100 fast mode plus 50 high - speed mode 10 t hd;dat data hold time standard mode 0 3.45 ? b < 100 pf 0 70 ns high - speed mode, c b < 400 pf 0 150 ns t rcl scl rise time standard mode 20+0.1c b 1000 ns fast mode 20+0.1c b 300 fast mode plus 20+0.1c b 120 high - speed mode, c b < 100 pf 10 80 high - speed mode, c b < 400 pf 20 160 continued on the following page
? 201 2 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 10 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support i 2 c timing specifications (continued) guaranteed by design. symbol parameter conditions min. typ. max. unit t fcl scl fall time standard mode 20+0.1c b 300 ns fast mode 20+0.1c b 300 fast mode plus 20+0.1c b 120 high - speed mode, c b < 100 pf 10 40 high - speed mode, c b < 400 pf 20 80 t rcl1 rise time of scl after a repeated start condition and after ack bit high - speed mode, c b < 100 pf 10 80 ns high - speed mode, c b < 400 pf 20 160 t rda sda rise time standard mode 20+0.1c b 1000 ns fast mode 20+0.1c b 300 fast mode plus 20+0.1c b 120 high - speed mode, c b < 100 pf 10 80 high - speed mode, c b < 400 pf 20 160 t fda sda fall time standard mode 20+0.1c b 300 ns fast mode 20+0.1c b 300 fast mode plus 20+0.1c b 120 high - speed mode, c b < 100 pf 10 80 high - speed mode, c b < 400 pf 20 160 t su;sto stop condition setup time standard mode 4 ? b capacitive load for sda and scl 400 pf
? 201 2 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 11 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support timing diagrams figure 5 . i 2 c interface timing for fast and slow modes figure 6 . i 2 c interface timing for high - speed mode start repeated start scl sda t f t hd; sta t low t r t hd;d at t high t su; dat t su; sta t hd; sto t buf start stop t hd; sta repeated start sclh sdah t fda t low t rcl1 t hd ;dat t high t su;s to repeated start t rda t fcl t su ;dat t rcl stop = mcs current source pull-up = r p resistor pull-up note a note a: first rising edge of sclh after repeated start and after each ack bit. t hd ;sta t su; sta
? 201 2 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 12 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support charge mode typical characteristics unless otherwise specified, circuit of figure 1 , v oreg = 4.2 v, v bus = 5.0 v, and t a = 25c. figure 7 . battery charge current vs. v bus with i bus lim =100 ma figure 8 . battery charge current vs. v bus with i bus lim =500 ma figure 9 . efficiency vs. v bus , i buslim =500 ma, i sys =0 figure 10 . efficiency vs. charging current , i buslim = n o l imit 80 90 100 110 120 130 140 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 battery charge current (ma) battery voltage v bat (v) 4.5 vbus 5.0 vbus 5.5 vbus 200 300 400 500 600 700 800 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 battery charge current (ma) battery voltage v bat (v) 4.5 vbus 5.0 vbus 5.5 vbus 65 70 75 80 85 90 95 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 efficiency (%) battery voltage v bat (v) 4.5 vbus 5.0 vbus 5.5 vbus 78 80 82 84 86 88 90 550 750 950 1150 1350 1550 efficiency (%) battery charge current i bat (ma) 4.5vbus, 3.9vbat 5.0vbus, 3.54vbat 5.0vbus, 4.2vbat 5.5vbus, 3.9vbat
? 201 2 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 13 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support charge mode typical characteristics unless otherwise specified, circuit of figure 1 , v oreg = 4.2 v, v bus = 5.0 v, and t a = 25c. figure 11 . charger startu p at v bus plug - in, 100 ma i buslim , 3.2 v bat , 100 sys load figure 12 . charger start u p at v bus plug - in, 500 ma i inbuslim , 3.2 v bat , 100 sys load figure 13 . charger start u p at v bus plug - in u sing 300 ma current limited source, 500 ma i buslim , 3.2 v bat , 50 ? sys load figure 14 . charger startup with hz bit reset, 500 ma i buslim , 950 ma i charge , 50 ?? sys load
? 201 2 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 14 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support charge mode typical characteristics unless otherwise specified, circuit of figure 1 , v oreg = 4.2 v, v bus = 5.0 v, and t a = 25c. figure 15 . battery removal / insertion while charging, te=0, 3.9 v bat , i chrg =950 ma, i buslim = n o l im i t , 50 sys load figure 16 . battery removal / insertion when charging, te=1, 3.9 v bat , i chrg =950 ma, i buslim = n o l i mit , 50 sys load figure 17 . no battery at v bus power - up, fan54040, 100 sys load, 1 k v bat l oad figure 18 . no battery at v bus power - up, fan54042, 100 sys load, 1 k v bat load
? 201 2 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 15 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support charge mode typical characteristics unless otherwise specified, circuit of figure 1 , v oreg = 4.2 v, v bus = 5.0 v, and t a = 25c. figure 19 . hz mode vbus current vs. temperature, 3.7 v bat figure 20 . v ref vs. load current, o ver - temperature, 5.0 v bus figure 21 . charging vs. temperature (ntc), +30 c to - 10 c 3.7 v bat , i chrg =950 ma, n o i buslim , 100 sys l oad figure 22 charging vs. temperature (ntc), +30 c to +7 0 c 3.7 v bat , i chrg =950 ma, n o i buslim, 100 sys l oad 0 200 400 600 800 1,000 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 high - z mode input current ( a) v bus input voltage (v) - 30c +25c +85c 1.00 1.20 1.40 1.60 1.80 2.00 0 1 2 3 4 5 v ref output voltage (v) v ref load current (ma) - 30c +25c +85c
? 201 2 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 16 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support gsm typical characteristics a 2.0 a gsm pulse applied at vbat with 5 s rise / fall time. simultaneous to gsm pulse, 50 additional load applied at sys. figure 23 . 2.0 a gsm pulse response, i bus lim =500 ma control, i chrg =950 ma, 3.7 v bat , oreg=4.2 v figure 24 . 2.0 a gsm pulse response, i bus lim =500 ma, i chrg =950 ma, 3.7 v bat , oreg=4.2 v, 200 ma source current limit
? 201 2 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 17 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support boost mode typical characteristics unless otherwise specified, using circuit of figure 1 , v bat =3.6 v, t a =25c. figure 25 . efficiency vs. i bus o ver v bat figure 26 . efficiency vs. i bus o ver - temperature, 3.6 v bat figure 27 . regulation vs. i bus o ver v bat figure 28 . output ripple vs. i bus o ver v bat figure 29 . quiescent current (i q ) vs. v bat o ver - temperature figure 30 . battery discharge current vs. v bat , hz / sleep mode 75 80 85 90 95 100 0 100 200 300 400 500 efficiency (%) v bus load current (ma) 2.7vbat 3.6vbat 4.2vbat 75 80 85 90 95 100 0 100 200 300 400 500 efficiency (%) v bus load current (ma) - 10c, 3.6vbat +25c, 3.6vbat +85c, 3.6vbat 4.85 4.90 4.95 5.00 5.05 5.10 5.15 0 100 200 300 400 500 output voltage v bus (v) v bus load current (ma) 2.7vbat 3.6vbat 4.2vbat 0 5 10 15 20 25 30 0 100 200 300 400 500 v bus ripple (mv pp ) v bus load current (ma) 2.7vbat 3.6vbat 4.2vbat 100 150 200 250 300 350 2 2.5 3 3.5 4 4.5 5 otg/boost quiescent current (a) battery voltage, v bat (v) - 30c +25c +85c 0 2 4 6 8 10 2 2.5 3 3.5 4 4.5 5 hz mode battery current (a) battery voltage, v bat (v) - 30c +25c +85c
? 201 2 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 18 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support boost mode typical characteristics unless otherwise specified, using circuit of figure 1 , v bat =3.6 v, t a =25c. figure 31 . otg start u p, 50 load, 3.6 v bat e xternal / a dditional 10 f o n vbus figure 32 . otg v bus overload response figure 33 . load transient, 20 - 200 - 20 ma i bus , t rise/fall = 100 ns figure 34 . line transient, 50 load, 3.9 - 3.3 - 3.9 v bat , t rise/fall = 10 s
? 201 2 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 19 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support circuit description / overview when charging batteries with a current - limited input source, such as usb, a switching chargers high efficiency over a wide range of output voltages minimizes charging time. fan 5404 x combines a highly integrated synchronous buck regulator for charging with a synchronous boost regula tor, which can supply 5 v to usb on - the - go (otg) peripherals. the fan5404x employs synchronous rectification for both the charger and boost regulators to maintain high efficiency over a wide range of battery voltages and charge states. the fan 5404 x has four operating modes: 1. charge mode: charges a single - cell li - i on or li - polymer battery . 2. boost mode: provides 5 v power to usb - otg with an integrated synchronous rectification boost regulator , using the battery as input. 3. high - impedance mode : both the boost and charging circuits are off in this mode. current flow from vbus to the batt ery or from the battery to vbus is blocked in this mode. this mode consumes very little current from vbus or the battery. 4. production test mode this mode provides 4. 2 v output on vbat and supplies a load current of up to 2.3 a. charge mode in c harge mode , fan 5404 x employs six regulation loops: 1. input current : limits the amount of current drawn from vbus. this current is sensed internally and can be programmed through the i 2 c interface . 2. charging current : limits the maximum charging current. this current is s ensed using an in ternal sense mosfet . 3. vbus voltage : this loop is designed to prevent the input supply from being dragged below v bus lim (typically 4.5 v) when the input power source is current limited. an example of this would be a travel charge r . this loop cuts back the current when v bus approaches v bus lim , allowing the input source to run in current limit. 4. charge voltage : the regulator is restricted from exceeding this voltage. as the internal battery voltage rises, the batterys internal impedance work s in conjunction with the charge voltage regulation to decrease the amount of current flowing to the battery . battery charging is completed when the current through q4 drops below the i term threshold . 5. power path: when v bat is below v batmin , q4 operates as a linear current source and modulates its current to ensure that the voltage on sys stays above 3.4 v. 6. temperature: if the ics junction temperature reaches 120c, charge current is reduced until the ics temperature is below 120c. battery charging c urve i f the battery voltage is below v short , a linear current source pre - charges the battery until v bat reaches v short . the pwm charging circuit is then started and the battery is charged with a constant current if sufficient input power is available. the curren t slew rate is limited to prevent overshoot. the fan 5404 x is designed to work with a current - limited input source at vbus. during the current regulation phase of charging, i bus lim or the programmed charging current limit s the amount of current available to charge the battery and power the system. the effect of i bus lim on i charge can be seen in figure 36 . f igure 35 . charge curve, i charge not limited by i inlim figure 36 . charge curve, i bus lim limits i charge assuming that v oreg is programmed to the cells fully charged float voltage, the current that the battery accept s with the pwm regulator limiting its output (sensed at vbat) to v oreg declines and the charger enters the voltage regulation phase of charging. when the current declines to the programmed i term value, the charge cycle is complete. charge current termination can be disabled by resetting the te bit ( reg1[3] ) . the charger output or float voltage can be programmed by the oreg bits from 3.5 v to 4.44 v in 20 mv incr ements, as shown in table 4 . i b a t i s h o r t c h a r g e c o n s t a n t c u r r e n t ( c c ) c o n s t a n t v o l t a g e ( c v ) p r e - c h a r g e r e - c h a r g e b a t t e r y v o l t a g e d e c a y i c h a r g e c u r r e n t c h a r g i n g v f l o a t i c h a r g e v s h o r t i s h o r t i t e r m v b a t v b a t m i n i o _ l e v e l i b a t i s h o r t c h a r g e c o n s t a n t c u r r e n t ( c c ) c o n s t a n t v o l t a g e ( c v ) p r e - c h a r g e r e - c h a r g e b a t t e r y v o l t a g e d e c a y i n p u t c u r r e n t l i m i t e d c h a r g i n g v b a t v f l o a t i c h a r g e i o _ l e v e l v b a t m i n v s h o r t i s h o r t i t e r m
? 201 2 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 20 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support the following charging parameters can be programmed by the host through i 2 c: table 3 . programmable charging parameters parameter name register output voltage regulation v oreg reg2[7:2] battery charging current limit i ochrg reg4[6: 3 ] input current limit i inlim reg1[7:6] charge termination limit i term reg4[2:0] weak battery voltage v lowv reg1[5:4] table 4 . oreg bits (oreg[7:2]) vs. charger v out (v oreg ) float v oltage decimal hex voreg decimal hex voreg 0 00 3.50 24 18 3.98 1 01 3.52 25 19 4.00 2 02 3.54 26 1a 4.02 3 03 3.56 27 1b 4.04 4 04 3.58 28 1c 4.06 5 05 3.60 29 1d 4.08 6 06 3.62 30 1e 4.10 7 07 3.64 31 1f 4.12 8 08 3.66 32 20 4.14 9 09 3.68 33 21 4.16 10 0a 3.70 34 22 4.18 11 0b 3.72 35 23 4.20 12 0c 3.74 36 24 4.22 13 0d 3.76 37 25 4.24 14 0e 3.78 38 26 4.26 15 0f 3.80 39 27 4.28 16 10 3.82 40 28 4.30 17 11 3.84 41 29 4.32 18 12 3.86 42 2a 4.34 19 13 3.88 43 2b 4.36 20 14 3.90 44 2c 4.38 21 15 3.92 45 2d 4.40 22 16 3.94 46 2e 4.42 23 17 3.96 47 - 63 2f - 3f 4.44 note: 9. default settings are denoted by bold typeface. provided dis, ce# and hz_mode are low , a new charge cycle begins when one of the following occurs: 1. the battery voltage falls below v oreg - v rch after charge termination has occurred. 2. any i 2 c write occurs causing the t32 s timer to run. products that include the auto - charge feature also begin charging if: 3. vbus power - on - reset (por) occurs and the battery voltage is below the weak battery threshold (v lowv ). charge c urrent l imit (i ocharge ) table 5 . i ocharge c urrent as f unction of i ocharge b its ( reg 4 [6:3] ) dec bin hex i ocharge (ma) 0 0000 0 550 1 0001 1 650 2 0010 2 750 3 0011 3 850 4 0100 4 950 5 0101 5 1,050 6 0110 6 1,150 7 0111 7 1,250 8 1000 8 1,350 9 1001 9 1,450 10 - 15 1010 - 1111 a - f 1,550 when the io_level bit is set (default), the i ocharge bits are ignored and charge current is set to 340 ma. pwm controller in charge mode the ic uses a current - mode pwm controller to regulate the output voltage and battery charge currents. the synchronous rectifier (q2) has a negative current limit that turns off q2 at 140 ma to prevent current flow from the battery. termination current limit current charge termination is enabled when te (reg1[3])=1. typical termination current values are given in table 6 . table 6 . termination current as function of iterm bits (reg4[2:0]) or pc_it bits (reg7[2:0] i term bits or pc_it bits termination current (ma) 0 50 1 100 2 150 3 200 4 250 5 300 6 350 7 400 when the charge current falls below i term; pwm charging stops, but the stat pin remains low . the stat pin then goes high and the status bits change to charge done (10), provided the battery and charger are still connected. a post - charging feature, top - off charging, is available to continue the battery charging to a lower charge current to maximize battery capacity. the pc _en bit must be set to 1 before the battery charging current reaches the termination current i term for normal charging. the post - charging termination current is set by the pc_it[2:0] bits, as shown in table 6 . if pc_en is set to 1; right after the normal charging is ended as described above, post charging is started with pc_on monitor bit set to 1. once the current reaches the
? 201 2 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 21 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support threshold for post - charging completion, pwm charging stops and pc_on bit changes back to 0. during post - charging , the stat pin is high , indicating that the charge current is below the i term level . to exit post - charging, one of the following must occur: a v bus por, the pok_b cycled when v bat <3.0 v , or the ce# or hz_mode bit cycled. safety timer at the beginning of charging, the ic starts a 15 - minute timer ( t 15 min ). when this timer times out , charging is terminated. writing to any register through i 2 c stops and resets the t 15 min timer, which in turn starts a 32 - second timer ( t 32 s ). setting the tmr_rst bit (reg0[7] ) resets the t 32 s timer. if the t 32 s timer times out ; charging is terminated, the registers are set to their default values, and charging resumes using the default values with the t 15 min timer running. normal charging is controlled by the host with the t 32 s timer running to ensure that the host is alive. charging with the t 15 min timer running is used for charging unattended by the host. if the t 15 min timer expires, the ic turns off the ch arger and indicates a timer fault (110) on the fault bits (reg0[2:0]). this sequence prevents overcharge if th e host fails to reset the t 32 s timer. v bus por / n on - c ompliant c harger r ejection 256 ms after vbus is connected , the ic pulse s the stat pin and set s the vbus_con bit . before starting to supply current, the ic applies a 110 ? load from vbus to gnd . v bus must remain above v in ( mi n) 1 and below vbus ovp for t vbus_valid (3 2 ms) bef ore the ic initiates charging or supplies power to sys . the v bus validation sequence always occurs before significant current is drawn from vbus (for example, after a vbus ovp fault or a v rch recharge initiation). t vbus_valid ensures that unfiltered 50/60 h z chargers and other non - compliant chargers ar e rejecte d. usb - friendly b oot s equence at v bus por, when the battery voltage is above the weak battery threshold ( v lowv ) ; the ic operates in accordance with its i 2 c register settings . if v bat < v lowv and t 32s is not running, the ic sets all registers to their default values and begins to deliver power to sys . fan54040 , fan54042 , and fan5404 7 feature auto - charge, which allow these parts to deliver charge to the battery prior to receiving host commands. fan54041 does not automatically initiate charging at v bus por . instead, it wait s in idle state for the host to initiate charging through i 2 c commands . while in idle state, q4 and q5 are on . this allows the system to run through a separate power path without requiring an additional disco nnection mosfet. power path operation as long as v bat < v batmin , q4 o perate s as a linear current source, ( power path mode ) with its current limited to 340 ma . the ic then regulate s sys to 3.54 v and attempt s to charge the battery with as much current as possible with the available i buslim input current, without allowing sys to drop below 3.4 v . this ensures that system power always receives first priority from a limited input supply . during this time, pok _b i s high . if v bat < v short , q4s current is further reduced to about 13 ma (i short ) when i buslim is set to 100 or 500 ma . for all other input current limits, i short current is approximately 30 ma. the pok _b signal can be used to keep the system in a low - power state, preventing excessive loading from the system while attempting to charge a depleted battery . table 7 . vbatmin thresholds to exit power path mode i buslim (ma) v batmin (v) 100 3.4 500 3.3 800 3.2 no limit 3.2 after v bat reache s v batmin , q4 close s and is used as a current - sense element to limit i charge per the i 2 c register settings by limiting the pwm modulators current ( f ull pwm m ode ). during pwm mode, if sys drops more than 5 mv (v thsys ) below v bat , q4 and q5 are tu rned on (gate is pulled low ) . once sys voltage becomes higher than v bat , q5 is turned off and q4 again serves as the current - sense element to limit i ocharge . q4 and q5 are both turned on when the ic enters sleep m ode (v bu s < v bat ). pok _b pulls low once v bat reaches v lowv , and remain s low as long as the ic is in f ull pwm m ode . the ic remain s in f ull pwm m ode as long as v bat > 3.0 v, at which point , the ic enter s power path charging mode . startup with a dead battery at v bus por, a 2 k ? load is applied to vbat for 256 ms to discharge any residual system capacitance in case the battery is absent or its discharge protection switch is open . if v bat < v lowv , all registers are reset to default values and th e ic charge s in t15min mode . if v bat < v short , the safety register is reset to its default value and the battery detection test below is performed. battery d etection if v bat is below v short when charging is enabled, the dbat_b bit is reset and the ic ( except FAN54045 and fan54046 ) performs an addition battery detection test. after v bat rises above v short , pwm charging begins (when ce# = 0) with the float voltage ( v oreg ) temporarily set to 4 v . if the battery voltage exceeds 3.7 v within 32 ms of the beginning of pwm charging, the battery is absent . if battery absence is detected: 1. stat pul s es, with fault bits set to 111 , and the nobat bit is set . 2. for fan54040 only ; the t 15 min timer is disabled until v bus is removed, idle state is entered , and pok_b remains high . 3. the i c bypass es the protection switch close test below, since no battery is present. the fan54042 and fan54047 continue to charge. if v bat remain ed below 3.7 v during th e initial 32 ms period, p ower p ath mode charging continues to ensure that the
? 201 2 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 22 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support batterys discharge protection switch has closed before exiting power path mode : 1. if v bat is less than 3.4 v, v sys is set to 4 v, and power path charging continues until v bat has exceeded 3.4 v for at least 1 28 ms . c harging continues until : 2. v bat has dropped below 3.2 v for at least 32 ms . once this occurs, v sys returns to the oreg register setting (default 3.54 v) . 3. v bat has again risen above v batmin for at least 4 ms . after these three events, pwm mode is entered and the ic sets the dbat_b bit . if the host sets the dbat _b bit (reg2[1]) , events 1 and 2 above are skipped and pwm mode is entered once v bat rises above v batmin . in a typical application, as soon as the host processor has cleared its uvlo threshold (typi cally 3.3 v), the hosts low level software would set the ibuslim and iocharge registers to charge the battery more rapidly above v batmin as soon as the host determines that more than 100 ma is available through vbus (see figure 37 ) . once the host processor begins writing to the ic, charge parameters are set by the host, which must continually reset the t 32s timer to continue charging using the programmed charging param eters. if t 32s times out ; the register defaults are loaded, the fault bits are set to 110, stat is pulsed, and charging continues with default charge parameters in t15min mod e for the fan54040, fan54042 , and fan54047. pok_b ( see table 8 ) the pok_b pin and bit are intended to provide feedback to the baseband processor that the battery is strong enough to allow the device to fully function . whenever the i c is operating in power path mode , pok_b is high . on exiting power path m ode, pok_b remain s high until v bat > v lowv . reg1[5:4] set s the v lowv threshold. the stat pin pulse s any time the pok_b pin changes. table 8 . q4 , q5, pok _b , and gate operation vs . charging mode q4 cc - cv control v bus v bat v sys q4 q5 gate pok _b power path mode : maintain v sys > 3.4 v valid < v batmin < 3.4 linear off high high power path mode : limit i charge < 34 0 ma valid < v batmin > 3.4 linear off high high pwm mode . q4 s enses c urrent for i charge valid > v batmin and < v lowv x on off high high > v lowv low off v batmin on off high on pwm mode 0 valid > v sys , >v batmin on on low on disabled 1 valid x off off high on power path charging 0 valid 2 v < v bat < v batmin linear off high off 30 ma linear charging x valid < 2 v bat on on low off off x x x on on low
? 201 2 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 23 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support figure 37 . recommended h ost s oftware s equence when b ooting with d ead b attery s y s t e m w a k e - u p h a l t l o a d l o w - l e v e l s o f t w a r e d e t e r m i n e u s b p o w e r a v a i l a b l e s e t i i n l i m p e r u s b p o w e r a v a i l a b l e , r e s e t i o _ l e v e l a n d s e t i o c h a r g e b i t s b a t t e r y i n s t a l l e d ? n o y e s n o 2 m i n u t e s e l a p s e d ? d e a d b a t b i t s e t ? y e s n o s e t d e a d b a t b i t y e s s e t a l l c h a r g e p a r a m e t e r s s e t s a f e t y r e g i s t e r s e t t m r _ r s t b i t e v e r y 1 0 s e c . p o k _ b = 0 ? y e s n o y e s l o a d f u l l f u n c t i o n a l i t y
? 201 2 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 24 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support battery temperature (ntc) monitor the fan5404x reduces the maximum charge current and termination voltage if an ntc measuring battery temperature (t bat ) indicates that it is outside the fast - charging limits (t2 to t3) , as described in the jeita specification 1 . there are four temperature thresholds that change battery charger operation: t1, t2, t3, and t4 , shown in table 10 . table 10 . battery temperature thresholds f or use with 10 k ntc, ? = 3380, and r ref = 10 k. threshold temperature % of v ref t1 0c 73.9 t2 10c 64.6 t3 45c 32.9 t4 60c 23.3 table 11 . charge parameters vs . t bat t bat (c) i charge v float below t1 charging to vbat disabled between t1 and t2 i ocharge / 2 ( 11 ) 4.0 v between t2 and t3 i ocharge v oreg between t3 and t4 i ocharge / 2 ( 11 ) 4.0 v above t4 charg ing to v bat disabled note: 11. if i ocharge is programmed to less than 650 ma, the charge current is limited to 340 ma. thermistors with other ? values can be used, with some shift in the corresponding temperature threshold, as shown in table 12 . table 12 . thermistor temperature thresho lds r ref = r thrm at 25c parameter various thermistors r thrm (25c) 10 k ? 1 japan electronics and information technology industries association (jeita) and battery association of japan . a guide to the safe use of secondary lithium ion batteries in notebook - type personal computers, april 28, 2007 . the host processor can disable temperature - driven control of charging parameters by writing 1 to the temp_dis bit . since temp_dis is reset whenever the ic resets its registers , the temperature controls ar e enforced whenever the ic is auto - charging, since auto - charge is always preceeded by a reset of registers . to d isable the thermistor circuit, tie the ntc pin to gnd . before enabling the charger, the ic tests to see if ntc is shorted to gnd . if ntc is shorted to gnd, no thermistor readings occur and the ntc_ok and ntc1 - ntc4 is reset. the ic first measures the ntc im mediately prior to entering any pwm charging state, then measures the ntc once per second, updating the result in ntc1 - ntc4 bits (reg 12h[3:0]). table 13 . ntc1 - ntc4 decoding t bat (c) ntc4 ntc3 ntc2 ntc1 above t4 1 1 1 1 between t3 and t4 0 1 1 1 between t2 and t3 0 0 1 1 between t1 and t2 0 0 0 1 below t1 0 0 0 0
? 201 2 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 25 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support flow charts figure 38 . charger v bus por f low c hart figure 39 . ready state f low c hart v b u s p o r y e s r e a d y s t a t e n o n o r e s e t a l l r e g i s t e r s s t a r t t 3 2 s e c h z s t a t e c h a r g e s t a t e y e s n o t 3 2 s e c a r m e d ? n o y e s h z o r d i s a b l e p i n s e t ? v b a t > v l o w v y e s h z , o r d i s a b l e p i n s e t ? t 3 2 s e c a r m e d ? n o y e s h z _ s t a t e v b a t > v l o w v ? y e s r u n t 3 2 s e c n o n o h z o r d i s a b l e p i n s e t ? y e s r e a d y s t a t e p w m = o f f q 4 , q 5 = o n n o t 3 2 s e c a r m e d ? y e s c h a r g e s t a t e
? 201 2 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 26 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support figure 40 . charge state flow chart y e s c h a r g e s t a t e y e s n o v b a t < v s h o r t v b a t < v s h o r t y e s l i n e a r c h a r g i n g r e s e t s a f e t y r e g v b u s o k ? i n d i c a t e t i m e r f a u l t i n d i c a t e c h a r g e c o m p l e t e b a t t e r y a b s e n t b e h a v i o r ? o f f p r o t e c t i o n s w i t c h c l o s e d ? n o e n a b l e p w m v b a t < v b a t m i n e n a b l e p o w e r p a t h c h a r g i n g c e # = 1 i d l e s t a t e n o t i m e r r u n n i n g ? y e s y e s n o y e s n o e n a b l e p w m c h a r g i n g i d l e s t a t e t 1 5 m i n t . o . o r [ t 3 2 s t . o . a n d f a n 5 4 0 4 1 ] ? i d l e s t a t e y e s i n d i c a t e v b u s f a u l t n o y e s b a t t e r y p r e s e n t ? n o b a t t e r y r e m o v e d r e s e t c h a r g e p a r a m e t e r s & s a f e t y r e g s y e s v b a t < v o r e g C v r c h ? c h a r g e s t a t e n o y e s n o n o i o u t < i t e r m a n d t e = 1 y e s p w m o n q 4 a n d q 5 o f f e n a b l e p w m f i r s t t i m e ? y e s n o d i s a b l e p w m f o r 2 s e c o n d s e o c = 1 n o y e s n o b a t t e r y p r e s e n t ? e n u n c i a t e b a t t e r y a b s e n t f a u l t n o c e # = 1 n o y e s o n y e s
? 201 2 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 27 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support figure 41 . hz state figure 42 . idle state s t o p t 3 2 s e c h z s t a t e n o s t a r t t i m e r a n d g o t o c h a r g e s t a t e v b a t > v l o w v ? y e s y e s r u n t 3 2 s e c r e s e t t 1 5 m i n i f r u n n i n g d i s p i n h i g h l o w n o h z _ m o d e o r d i s p i n s e t ? p w m = o f f q 4 , q 5 = o n t i m e r a r m e d ? y e s n o i d l e s t a t e h z s t a t e y e s n o h z o r d i s a b l e p i n s e t ? y e s i d l e s t a t e p w m = o f f q 4 , q 5 = o n n o t 3 2 s e c a r m e d ? c h a r g e s t a t e
? 201 2 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 28 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support figure 43 . timer flow chart for fan54040, fan54042 , fan54047 figure 44 . timer flow chart for fan54041 input current limiting to minimize charging time without overloading vbus current limitations, the ics input current limit can be programmed by the i bus lim bits (reg1[7:6]). table 14 . input current limit i bus lim reg1[7:6] input current limit 00 100 ma 01 500 ma 10 800 ma 11 no limit for the fan54041 , no charging occurs automatically at vbus por, so the input current limit is established by the i bus lim bits. vbus control loop the ic includes a control loop that limit s input current in case a current - limited source is supplying v bus . the control increases the charging current until either: ? i bus lim or i ocharge is reached or ? v bus = v buslim . if v bus collapses to v buslim , the vbus loop reduces its current to keep v bus = v buslim . when the vbus control loop is limiting the charge current , the vlim bit (reg 5[ 3 ]) is set. c h a r g e s t a r t s t a r t t 1 5 m i n t 1 5 m i n a c t i v e ? r e s e t r e g i s t e r s y e s n o s t a r t t 3 2 s e c s t o p t 1 5 m i n i 2 c w r i t e r e c e i v e d ? y e s t 1 5 m i n e x p i r e d ? n o c o n t i n u e c h a r g i n g t 3 2 s e c e x p i r e d ? y e s n o n o y e s t i m e r f a u l t p w m = o f f c h a r g e s t a r t f r o m h o s t c o n t r o l c h a r g e t 3 2 s e c e x p i r e d ? y e s t i m e r f a u l t s t o p p w m a n d r e s e t r e g i s t e r s t m r _ r s t b i t s e t ? r e s e t t 3 2 s e c y e s n o n o
? 201 2 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 29 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support table 15 . v bus limit as f unction of v buslim b its (reg5[2:0]) v buslim (reg5[2:0] ) dec bin hex v buslim 0 000 0 4.213 1 001 1 4.293 2 010 2 4.373 3 011 3 4.453 4 100 4 4.533 5 101 5 4.613 6 110 6 4.693 7 111 7 4.773 safety s ettings the ic contain s a safety register (reg6) that prevents the values in oreg ( reg2[7:2] ) and iocharge (reg4[ 7 :4]) from exceeding the values of the vsafe and isafe values . after v bat rises above v short , the safety register i s loaded with its default value and may be written to only before writing to any other register. the same 8 - bi t value should be written to the safety register twice to set the register value . after writing to any other register, the safety register is locked until v bat falls below v short . the isafe (reg6[ 7 :4]) and vsafe (reg6[3:0]) registers establish values that limit the maximum values of i ocharge and v oreg used by the control logic. if the host attempts to write a value higher than vsafe or isafe to oreg or iocharge , respectively ; the vsafe, isafe value appear s as the oreg, iocharge register value , respectively. table 16 . maximum i ocharge as f unction of isafe b its ( reg6[ 7 :4] ) dec bin hex i ocharge (max) (ma) 0 0000 0 550 1 0001 1 650 2 0010 2 750 3 0011 3 850 4 0100 4 950 5 0101 5 1,050 6 0110 6 1,150 7 0111 7 1,250 8 1000 8 1,350 9 1001 9 1,450 10 - 15 1010 - 1111 a - f 1,550 table 17 . v safe (v oreg limit) as function of vsafe bits ( reg6[3:0] ) vsafe (reg6[3:0]) dec bin hex oreg max. (reg2[7:2]) voreg max. 0 0000 0 100011 4.20 1 0001 1 100100 4.22 2 0010 2 100101 4.24 3 0011 3 100110 4.26 4 0100 4 100111 4.28 5 0101 5 101000 4.30 6 0110 6 101001 4.32 7 0111 7 101010 4.34 8 1000 8 101011 4.36 9 1001 9 101100 4.38 10 1010 a 101101 4.40 11 1011 b 101110 4.42 12 - 15 1100 - 1111 c - f 101111 - 110010 4.44 thermal regulation and p rotection when the ics junction temperature reaches t cf (about 120c) , the charger reduces its output current to 550 ma to prevent overheating. if the temperature increases beyond t shutdown ; charging is suspended , the fault bits ar e set to 101 , and stat is pulsed high . in s uspend m ode , all timers stop and the state of the ics logic is preserved. charging resumes at programmed current after the die cools to about 1 2 0c. additional ? ja data points , measured using the fan 5404 0 evaluation board , are given in table 18 (measured with t a = 25c). note that as power dissipation increases, the effective ? ja decreases due to the larger diff er ence between the die temperature and ambient. table 18 . evaluation board measured ? ja power (w) ? ja ? 0.504 54c/w 0.844 50c/w 1.506 46c/w
? 201 2 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 30 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support charge mode i nput s upply p rotection sleep m ode when v bus falls below v bat + v slp and v bus is above v in(min) , the ic enters sleep mode to prevent the battery from draining into vbus. during s leep m ode, reverse current is disabled by body switching q1. input s upply l ow - v oltage d etection the ic continuously monitors v bus during charging. if v bus falls below v in(min) , the ic : 1. terminates charging 2. pulses the stat pin , sets the stat us bits to 11, and sets the fault bits to 011 . i f v bus recovers above the v in(min) rising threshold after time t int (about two seconds), the charging process is repeated . this function prevents the usb power bus from collapsing or oscillating when the ic is connected to a suspended usb port or a low - current - capable otg device. input over - v oltage d etection when the v bus exceeds vbus ovp , the ic: 1. turn s off q3 2. suspend s chargin g 3. set s the fault bits to 001 , sets the status bits to 11, and pulses the stat pin . when v bus falls about 100 mv below vbus ovp , the fault is cleared and charging resumes after v bus is revalidated (see v bus por / n on - c ompliant c harger r ejection ) . vbus short while charging if vbus is shorted with a very low impedance while the ic is charging with i bus limit = 100 ma, the ic may not meet datasheet specifications until power is removed. t o trigger this condition, v bus must be driven from 5 v to gnd with a high slew rate. a chiev ing th is slew rate require s a 0 ? short to the usb cabl e less than 10 cm from the connector. sys short during discharge / supplemental mode caution should be taken to ensure the sys pin is not shorted when connected to a battery . this condition can induce high current flow through the batfet (q4) until the batterys own safety circuit trips . the resulting high current can damage the ic. charg e mode battery detection & protection v bat over - v oltage p rotection the oreg voltage regulation loop prevents v bat from overshooting v oreg by more than 50 mv when the battery is removed. when the pwm charger run s with no battery , the te bit is not set and a battery is inserted that i s charged to a voltage higher than v ore g ; pwm pulses stop. if no further pulses occur for 30 ms , the ic set s the fault bits to 100, sets the status bits to 11, and pulse s the stat pin . battery d etection d uring c harging th e ic can detect the presence, absence, or removal of a battery if the termination bit (te) is set and ce# = 0 . during normal charging, once v bat is close to v oreg and the charge current falls below i term ; the pwm charger continues to provide power to sys a nd q4 is turned off . it then turns on a discharge current, i detect , for t detect . if v bat is still above v oreg C v rch , the battery is present and the ic sets the status bits to 10 (charge done) . if v bat is below v oreg C v rch , the battery is absent and the ic: 1. sets the charging parameters to their default values . 2. sets the fault bits to 111 (battery absent) and sets the nobat bit . 3. if eoc=0, the ic t urns off the pwm for t int , then resumes charging . if the battery is still absent, the battery absent fault is then re - enunciated every t int . 4. if eoc = 1, the pwm remains on to provide power to sys, but charge termination and the battery absent test ar e performed every t int . linear charging if the battery voltage is below the short - circuit threshold (v short ) ; a linear current source, i s hort , charges v bat until v bat > v short . for i buslim settings of 100 ma or 500 ma, the linear charging current is typically 13 ma. for higher i buslim settings, the linear charging current is increased to 30 ma. charger status / f ault status the stat pin indicates the operating condition of the ic and provides a fault indicator for interrupt driven systems . table 19 . stat p in f unction en_stat charge state stat p in 0 x open x normal conditions open 1 charging low x fault ( charging or boost ) 128 ? s pulse , then open the fault bits (r0[2:0]) indicate the type of fault in charge mode (see table 28 ). production test mode (ptm) ptm provides 4.2 v at up to 2.3 a to vbat when v bus = 5.5 v 5%. the ic enters ptm when the prod bit is set and the nobat bit is high , indicating that the ic has detected battery absence . a battery absence detection test after vbus por is performed automatically for fan54040 , fan540 42 , and fan54047 only. a battery - absent detection test can be performed at any time by setting the te bit , setting v oreg to at least 4.0 v, then resetting the ce# bit . if no battery is present ; charge termination occur s , followed by a battery absent test, which set s the nobat bit . battery - absence detection is completed within 500 ms from the time that ce# is set.
? 201 2 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 31 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support in ptm, gate is low , q4 and q5 are on, and all auxiliary control loops are disabled . only the oreg loop is active, which controls v bat to 4.2 v , regardless of the oreg register setting . thermal shutdown remains active. during ptm, high current pulses ( load currents greater than 1.5 a) must be limited to 20% duty cycle with a m in imum period of 10 ms. charge mode control bits setting either hz_mode through i 2 c or dis pin to high disables the charger , puts the ic into h igh - i mpedan ce m ode , and stops t 32s . if v bat < v lowv while in h igh - i mpedance m ode, t 32s begins running and , when it overflows, all r egisters (except safety) reset, which enable s t 15min charging on versions with the 15 - minute timer if dis=0 . when t 15min overflows , the ic enters h igh - i mpedance m ode (idle) . a new charge cycle can only be initiated through i 2 c or vbus por. setting the reset bit clears all registers. if hz_mode bit was set w hen the reset bit is set, this bit is also cleared, but the t 32s timer is not started and the ic remain s in h igh - i mpedance m ode . table 20 . dis p in and hz_mode b it f unctionalit y charging dis pin hz_mode enable 0 0 disable x 1 disable 1 x raising the dis pin stops t 32s from advancing, but does not reset it. if the dis pin is raised during t 15min charging, the t 15min timer is reset. ce# determine s whether charging to v bat is enabled or not. boost mode b o ost m ode can be enabled if the ic is in 32 - s econd m ode by setting the opa_mode bit high and clearing the hz_mode bit. table 21 . enabling b oost hz_mode opa_mode boost 0 1 enabled 1 x disabled x 0 disabled t o remain in boost mode , the tmr_rst must be set by the host before the t 32s timer times out. if t 32s times out in b oost m ode ; the ic re sets all registers, pulses the stat pin, sets the fault bits to 110, and resets the boost bit. vbus por or reading r0 clears the fault condition . boost pwm c ontrol the ic uses a minimum on - time and computed minimum off - time to regulate v bus . the regulator achieves excellent transient response by employing current - mode modulation. this technique causes the regulator to exhibit a load line. during pwm m ode, the output voltage drops slightly as the input current rises. with a constant v bat , this appears as a constant output resistance. the droop caused by the output resistance when a loa d is applied allows the regulator to respond smoothly to load transients with no undershoot from the load line. this can be seen in figure 33 and figure 45 . figure 45 . output resistance (r out ) v bus as a function of i load can be computed when the regulator is in pwm mode (continuous conduction) as: eq. 1 at v bat =3.0 v and i load =300 ma, v bus drop s to: eq. 2 at v bat =3.6 v and i load =500 ma, v bus drop s to: eq. 3 pfm mode if v bus > vref boost ( nominally 5.0 7 v) when the minimum off - time end s , the regulator enters pfm m ode. boost pulses are inhibited until v bus < vref boost . the minimum on - time is increased to enable the output to pump up sufficiently with each pfm boost pulse. therefore , the regulator behaves like a constant on - time regulator, with the bottom of its output voltage ripple at 5.0 7 v in pfm m ode. table 22 . boos t pwm operating s tates mode description invoked when lin linear s tartup v bat > v bus ss boost s oft - s tart v bus < v bst bst boost o perating m ode v bat > uvlo bst and ss c ompleted startup when the boost regulator is shut down, current flow is prevented from v bat to v bus , as well as reverse flow from v bus to v bat . load out out i r v ? ? ? 07 . 5 v v out 98 . 4 3 . 0 30 . 0 07 . 5 ? ? ? ? v v out 95 . 4 5 . 0 24 . 0 07 . 5 ? ? ? ? 200 240 280 320 360 400 2.0 2.5 3.0 3.5 4.0 4.5 v bus output resistance (m ? ) battery voltage, v bat (v)
? 201 2 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 32 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support lin state when en rises, if v bat > uvlo bst ; t he regulator first attempt s to bring pmid within 4 00 mv of v bat using an internal 450 ma current source from vbat (lin state ). i f pmid has not achieved v bat C 400 mv after 5 60 ? s , a fault state is initiated. ss state when pmid > v bat C 400 mv , the boost regulator begins switching with a reduced peak current limit of about 50 % of its normal current limit. the output slews up until v bus is within 5 % of its s etpoint ; at which time , the regulation loop is closed and the current limit is set to 100%. if the output fails to achieve 9 5 % of its setpoint (v bst ) within 1 28 ? s, the cur rent limit is increased to 100% . if the output fails to achieve 9 5 % of its setpoint after this second 384 ? s period, a fault state is initiated. bst state this is the normal operating mode of the regulator. the regulator uses a minimum t off - minimum t on modulation scheme. the minimum t off is proportional to , which keeps the regulators switching frequency reasonably constant in ccm. t on (min) is proportional to v bat and is a higher value if the inductor current reached 0 before t off(min) in the prior cycle. to ensure v bus does not overshoot the regulation point, the boos t switch remain s off as long as v fb > v ref (bst) . boost faults if a boost fault occurs: 1. t he stat pin pulses . 2. opa_mode bit is reset . 3. the power stage is in high - impedance m ode . 4. the fault bits ( reg0[2:0] ) are set per table 23 . restart after boost faults opa_mode is reset on boost faults . b oost m ode can only be re - enabled by setting the opa_mode bit. table 23 . fault b its during b oost m ode fault bit fault d escription b2 b1 b0 0 0 0 normal (no fault) 0 0 1 v bus > vbus ovp 0 1 0 v bus fails to achieve the voltage required to advance to the next state during soft - start or sustained (>50 ? s) current limit during the bst state. 0 1 1 v bat < uvlo bst 1 0 0 na: this code does not appear . 1 0 1 thermal shutdown 1 1 0 timer fault ; a ll registers reset . 1 1 1 na: this code does not appear . monitor register s ( reg 10h , reg11h ) a dditional status monitoring bits enable the host processor to have more visibility into the status of the ic. the monitor bits are real - time status indicators and are not internally debounced or otherwise time qualified. the state of the monitor register bits listed in high - impedance m ode is valid only when v bus is valid. i 2 c interface the fan 5404 x s serial interface is compatible with s tandard, f ast, fast plus, and h igh - s peed m ode i 2 c bus specifications. the fan 5404 x scl line is an input and the sda line is a bi - directional open - drain output; it can only pull down the bus when active. the sda line only pulls low during data reads and when signaling ack. all data is shifted in msb (bit 7) first. slave address table 24 . i 2 c slave address byte 7 6 5 4 3 2 1 0 1 1 0 1 0 1 1 in hex notation, the slave address assumes a 0 lsb. the hex slave address is d6h for all parts in the family . other slave addresses can be accommodated upon request . contact a fairchild semiconductor representative. bus timing as shown in figure 46 , data is normally transferred when scl is low . data is clocked in on the rising edge of scl. typically, data transitions shortly at or after the falling edge of scl to allow ample time for th e data to set up before the next scl rising edge. figure 46 . data transfer timing each bus transaction begins and ends with sda and scl high. a transaction begins with a start condition, which is define d as sda transitioning from 1 to 0 with scl high , as shown in figure 47 figure 47 . start bit s c l t s u t h s d a d a t a c h a n g e a l l o w e d s c l t h d ; s t a s d a s l a v e a d d r e s s m s b i t out in v v w r/
? 201 2 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 33 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support transactions end with a stop condition, which is sda transitioning from 0 to 1 with scl high , as shown in figure 48 . figure 48 . stop bit during a read from the fan 5404 x ( figure 51 ), the master issues a repeated start after sending the register address and before resending the slave address. the repeated start is a 1 - to - 0 transition on sda while scl is high , as shown in figure 49 . high - speed (hs) mode the protocols for high - speed (hs), low - speed (ls), and fast - speed (fs) m odes are identical except the bus speed for hs m ode is 3.4 mh z. hs m ode is entered when the bus master sends the hs master code 00001xxx after a start condition. the master code is sent in fast or fast plus m ode (less than 1 mhz clock) ; slaves do not ack th e transmission. the master then generates a repeated start condition ( figure 49 ) that causes all slaves on the bus to switch to hs m ode. the master then sends i 2 c packets, as described above, using the hs m ode clock rate and timing. the bus remains in hs m ode until a sto p bit ( figure 48 ) is sent by the master. while in hs m ode, packets are separated by repeated start conditions ( figure 49 ). figure 49 . repeated start timing read and write transactions the figures below outline the sequences for data read and write. bus control is signified by the shading of the packet, defined as and . all addresses and data are msb first. table 25 . bit definitions for figure 50 - figure 53 symbol definition s start, see figure 47 a ack. the slave drives sda to 0 to acknowledge the preceding packet. nack. the slave sends a 1 to nack the preceding packet. r repeated start, s ee figure 49 p stop, se e figure 48 multi - byte ( sequential ) read and write transactions sequential write ( figure 52 ) the slave address, reg addr address , and the first data byte are transmitted to th e fan5404x in the same way as in a byte write ( figure 50 ) . however, instead of generating a stop condition, the master transmits additional bytes that are written to consecutive sequential registers after the falling edge of the eight h bit . after the last byte written and its ack bit received, the master issues a stop bit . the ic contains an 8 - bit counter that increments the address pointer after each byte is written. sequential read ( figure 53 ) sequential reads are initiated in the same way as a single - byte read ( figure 51 ) , except that once the slave transmits the first data byte, the master issues an acknowledge instead of a stop condition. this directs the slaves i 2 c logic to transmit the next sequentially addressed 8 - bit word . the fan5404x contains an 8 - bit counter that increments the address pointer after each byte is read, which allows the entire memory contents to be read during one i 2 c transaction. figure 50 . single - byte write transaction figure 51 . single - byte read trans a ction figure 52 . multi - byte ( sequential ) write transaction figure 53 . multi - byte ( sequential ) read transaction s c l s d a s l a v e r e l e a s e s m a s t e r d r i v e s a c k ( 0 ) o r n a c k ( 1 ) t h d ; s t o s c l s d a a c k ( 0 ) o r n a c k ( 1 ) s l a v e r e l e a s e s s l a d d r m s b i t t h d ; s t a t s u ; s t a master drives bus slave drives bus a
? 201 2 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 34 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support register descriptions the eight user - accessible ic registers are defined in table 26 . table 26 . i 2 c register address register address bits name reg# 7 6 5 4 3 2 1 0 control0 0 h 0 0 0 0 0 0 0 0 control1 1 h 0 0 0 0 0 0 0 1 oreg 2 h 0 0 0 0 0 0 1 0 ic_info 3 h 0 0 0 0 0 0 1 1 ibat 4 h 0 0 0 0 0 1 0 0 vbus_control 5 h 0 0 0 0 0 1 0 1 safety 6 h 0 0 0 0 0 1 1 0 post_charging 7 h 0 0 0 0 0 1 1 1 monitor 0 10h 0 0 0 1 0 0 0 0 monitor 1 1 1 h 0 0 0 1 0 0 0 1 ntc 1 2 h 0 0 0 1 0 0 1 0 wd_control 13h 0 1 1 0 1 1 0 0 table 27 . register bit definitions this table defines the operation of each register bit for all ic versions. default values are in bold text. bit name value type description control0 register address: 00 default value = 0100 0000 7 tmr_rst 0 w writing a 1 resets the t 32s timer ; w riting a 0 has no effect . reading this bit always returns 0 6 en_stat 0 r/w prevent s stat pin from going low during charging ; stat pin still pulses to enunciate faults 1 enables stat pin to be low when ic is charging 5:4 stat 00 r ready 01 pwm enabled . charging is occurring if ce# = 0. 10 charge done 11 fault 3 boost 0 r ic is not in boost mode 1 ic is in boost m ode 2:0 fault r table 28 . charger mode faults fault bit fault d escription 2 1 0 0 0 0 normal (no fault) 0 0 1 vbus ovp 0 1 0 sleep mode 0 1 1 poor input source 1 0 0 battery ovp 1 0 1 thermal shutdown 1 1 0 timer fault 1 1 1 no battery for boost mode faults, see table 23
? 201 2 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 35 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support bit name value type description control1 register address: 01 default value = 0 0 11 0 x 00 7:6 i bus lim r/w input current limit ; defaults to 00 (100 ma ) , s ee table 14 5:4 v lowv 00 r/w 3.4 v weak battery voltage threshold 01 3.5 v 10 3.6 v 11 3.7 v 3 te 0 r/w disable charge current termination 1 enable charge current termination 2 ce# 0 r/w charg ing enabled . default for fan54040, fan 54042 , fan54047 . 1 charg ing disabled . default for fan54041 , fan5404 5 , fan54046. 1 hz_mode 0 r/w not high - i mpedance m ode se e table 21 1 high - i mpedance m ode 0 opa_mode 0 r/w charge mode 1 boost m ode oreg register address: 02 default value = 0000 10 00 (0 8 h) 7:2 oreg r/w charger output float voltage ; p rogrammable from 3.5 to 4.44 v in 20 mv increments ; defaults to 000010 (3.54 v) , see table 4 . 1 dbat_b 0 r/w indicates that the ic detected a dead battery after vbus_por and that the charger has not yet completed the three steps to ensure that the batterys protection switch is closed if a battery is present , as described in the dead battery section on page 21 . writing a 0 to this bit is ignored. 1 the ic set s this bit to 1 if any of the following are true: 1. dead battery (v bat < v short ) was not detected at vbus_por. 2. the ic has completed the three steps to ensure that if the battery is present, the batterys protection switch has closed, as described in the dead battery section on page 21 . if the host sets this bit while the ic is charging the battery and dbat_b is low , the three steps are aborted and normal power path or pwm charging proceed s . 0 eoc 0 r/w if no battery is detected when a full battery (end of charge) is reached, pwm stop s , q4 and q5 remain on, and the charger automatically restart s after two seconds with te and ce# bits unchanged . 1 if no battery is detected when a full b attery (end of charge) is reached, the pwm charger stay s on, allowing the host processor to continue to run with no battery. ic_info register address: 03 default value = 100x xxxx 7: 6 vendor code 10 r identifies fairchild semiconductor as the ic supplier 5 : 3 pn r part number bits , see the ordering info on page 2 2 : 0 rev r ic revision , r evision 1.x , where x is the decimal of these three bits ibat register address: 04 default value = 1000 0 001 (8 1 h) 7 reset 1 w writing a 1 resets all registers , except the safety register (reg6), to their defaults : w riting a 0 has no effect ; r ead returns 1 6: 3 iocharge table 5 r/w programs the maximum charge current , see table 5 2:0 iterm table 6 r/w sets the current used for charging termination , see table 6
? 201 2 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 36 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support bit name value type description vbus_control register address: 05 default value = 0 01x x 100 7 reserved 0 r this bit always returns 0 6 prod 0 r/w charger operates in n ormal m ode. 1 charger operates in production test m ode . 5 io_level 0 r/w battery current is controlled by iocharge bits . 1 battery current control is set to 340 ma . 4 vbus_con r 1 indicates that v bus is above 4. 4 v (rising) or 3.8 v (falling) . when vbus_con changes from 0 to 1, a stat pulse occurs. 3 sp 0 r vbus control loop is not active (v bus is able to stay above v buslim ) 1 vbus control loop is active and v bus is being regulated to v buslim 2:0 vbuslim table 15 r/w vbus control voltage reference , see table 15 safety register address: 06 default value = 0100 0000 (40h) 7 :4 isafe table 16 r/w sets the maximum i ocharge value used by the control circuit , see table 16 3:0 vsafe table 17 r/w sets the maximum v oreg used by the control circuit , see table 17 post_charging register address: 07 default value =0000 0 001 (0 1 h) 7:6 bdet r/w these bits determine whether a battery absent detection will be performed when the ntc reading indicates out - of - range when charging. [7:6] when ntc goes out - of - range 00 always do battery absent detection 01 disable detection in n ormal m ode 10 disable detection when reg fa = b5 (pwm running after c harge d one . 11 ntc out - of - range in c harge d one does not cause battery absent detection. 5:4 vbus_load 0 r/w after charger termination, in the charge done state, these bits control vbus loading to improve detection of ac power removal from the ac adapter. [5:4] vbus loading in charge done state: 00 none 01 load vbus for 4 ms every two seconds 10 load vbus for 131 ms every two seconds 11 load vbus for 135 ms every two seconds 3 pc_en 0 r/w post charging or background charging feature is disabled 1 post charging or background charging feature is enabled 2:0 pc_it table 6 r/w sets the termination current for post or underground charging , se e table 6 monitor 0 register address: 10h (16) default value =xxx0 xxxx (xx h) 7 iterm_cmp r iterm comparator output , 1 when i charge > i ter m r eference 6 vbat_cmp r output of vbat comparator , 1 when v bat < v bus 5 linchg r 1 when 30 ma l inear charger on (v bat < v short ) 4 t_120 r thermal regulation comparator , 1 when the die temperature is greater than 120c . during this condition, charge current is limited to 340 ma. 3 ichg r 0 indicates the icharge loop is controlling the battery charge current . 2 ibus r 0 indicates the ibus (input current) loop is controlling the battery charge current . 1 vbus_valid r 1 indicates v bus has passed validation and is capable of charging . 0 cv r 1 indicates the constant - voltage loop (oreg) is controlling the charger and all current limiting loops have released .
? 201 2 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 37 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support bit name value type description monitor 1 register address: 1 1 h (1 7 ) default value =xx1x xxxx 7 gate 0 r gate pin is low , q5 is driven on. 1 gate pin is high , q5 is off. 6 vbat 0 r v bat < v batmin in pp charging, v bat < v low in pwm charging 1 v bat > v batmin in pp charging, v bat > v low in pwm charging 5 pok_b 0 r/w pok_b pin is low . 1 pok_b pin is high . writing to this bit sets the pok_b pin. 4 dis _level 0 r dis pin is low . 1 dis pin is high . 3 nobat 1 r battery absence 0 battery presence 2 pc_on 1 r post charging (background charging) is under progress . 0 post charging (background charging) is not under progress . 1:0 reserved 0 r these bits always return 0 . ntc register address: 1 2 h (1 8 ) default value =000x xxxx 7:6 reserved 00 r these bits always return 0 . 5 temp_dis 0 r/w ntc temperature measurement results affect charge parameters . 1 ntc temperature measurement results do not affect charge . temperature measurements continue to be updated every second in the ntc1 - 4 monitor bits. 4 ntc_ok r 0 if ntc is either shorted to gnd , open, or shorted to ref . 3 ntc4 r 1 indicates that ntc is above the t4 threshold . see table 10 C table 13 2 ntc3 r 1 indicates that ntc is above the t3 threshold . 1 ntc2 r 1 indicates that ntc is above the t2 threshold . 0 ntc1 r 1 indicates that ntc is above the t1 threshold . wd_control register address: 13 h (1 9 ) default value = 0 1 1 0 110 0 7 reserved 0 r /w these bits do not change the function of the ic . 6:5 reserved 1 1 r /w these bits do not change the function of the ic . 4 reserved 0 r /w these bits do not change the function of the ic . 3 reserved 1 r /w these bits do not change the function of the ic . 2 en_vreg 0 r/w vreg is off 1 vreg is on 1 wd_dis 0 r/w watchdog timer (t32s) operation normal 1 watchdog timer (t32s) disabled. 0 reserved 0 r this bit always returns 0 restart register address: fa h ( 250 ) default value = 1111 1111 7:0 restart w writing b5h restart s charging when the ic is in the charge done state . this register reads back ff .
? 201 2 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 38 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support pcb layout recommendatio n bypass capacitors should be placed as close to the ic as possible. in particular, the total loop length for c mid should be minimized to reduce overshoot and ringing on the sw, pmid, and vbus pins. power and ground pins should be routed directly to their bypass capacitors using the top copper layer. the c opper ar ea connecting to the ic should be maximized to improve thermal performance. see the layout recommendations in figure 54 . figure 54 . pcb layout recommendation
? 201 2 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 39 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support physical dimension s figure 55 . 25 - ball wlcsp, 5x5 array, 0.4 mm pitch, 250 m ball product - specific dimensions product d e x y fan 5404x uc x 2 . 4 0 0.030 2.00 0.030 0.180 0.380 package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner w ithout notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to verify or obtain the most recent revision. package specifications do not expand the terms of fairchilds worldwide terms and conditions, specifically t he warranty t herein, which covers fairchild products. always visit fairchild semiconductors online packaging area for the most recent package drawings: http://www.fairchildsemi.com/dwg/uc/uc025aa.pdf . b a l l a 1 i n d e x a r e a 1 2 3 4 5 a b c d e s e a t i n g p l a n e 2 5 x a 1 0 . 0 0 5 c a b f ? 0 . 2 6 0 0 . 0 2 0 . 4 0 1 . 6 0 0 . 4 0 1 . 6 0 ( x ) 0 . 0 1 8 ( y ) 0 . 0 1 8 e d 0 . 0 6 c 0 . 0 5 c e d f 0 . 3 7 8 0 . 0 1 8 0 . 2 0 8 0 . 0 2 1 n o t e s : a . n o j e d e c r e g i s t r a t i o n a p p l i e s . b . d i m e n s i o n s a r e i n m i l l i m e t e r s . c . d i m e n s i o n s a n d t o l e r a n c e p e r a s m e y 1 4 . 5 m , 1 9 9 4 . d . d a t u m c i s d e f i n e d b y t h e s p h e r i c a l c r o w n s o f t h e b a l l s . e . p a c k a g e n o m i n a l h e i g h t i s 5 8 6 m i c r o n s 3 9 m i c r o n s ( 5 4 7 - 6 2 5 m i c r o n s ) . f . f o r d i m e n s i o n s d , e , x , a n d y s e e t a b l e b e l o w . g . d r a w i n g f i l n a m e : m k t - u c 0 2 5 a a r e v 2 . 0 . 0 3 c 2 x 0 . 0 3 c 2 x c b a 0 . 6 2 5 0 . 5 4 7 0 . 4 0 1 . 6 0 0 . 4 0 1 . 6 0 ( ? 0 . 2 0 0 ) c u p a d ( ? 0 . 3 0 0 ) s o l d e r m a s k r e c o m m e n d e d l a n d p a t t e r n ( n s m d p a d t y p e ) t o p v i e w b o t t o m v i e w s i d e v i e w s
? 201 2 fairchild semiconductor corporation www.fairchildsemi.com fan54040 C fan54047 ? rev. 1.0.2 40 fan54040 - fan54047 usb - otg,1.55 a li - ion switching charger with power path and 2.3 a production test support
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